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seiko epson corporation 1 pf654-05 E0C6247 4-bit single chip microcomputer low voltage operation products n description the E0C6247 is a cmos 4-bit single chip microcomputer, built-in core cpu e0c6200a as main component, rom, ram, dot matrix lcd driver, serial interface, time base counter, svd circuit and others. the E0C6247 is most suitable for applications with equipment requiring dot matrix display functions. n features l cmos lsi 4-bit parallel processing l twin clock .............................................crystal oscillation circuit (with built-in drain capacitance) 32.768khz, 38.4khz, 50khz, 76.8khz ceramic or cr oscillation circuit 200khz (typ.) / 0.9v, 1mhz (max.) / 3.0v l instruction set ........................................ 108 instructions l instruction cycle time ............................ 32.768khz clock : 153 m sec, 214 m sec, 366 m sec 38khz clock : 130 m sec, 182 m sec, 313 m sec 50khz clock : 100 m sec, 140 m sec, 240 m sec 76khz clock : 65 m sec, 91 m sec, 156 m sec 200khz clock : 25 m sec, 35 m sec, 60 m sec l rom ...................................................... 8,192 12 bits l ram ...................................................... data : 1,792 4 bits segment : 256 4 bits l external memory ................................... read/write (ram) : 512k 4 bits (max.) read only (rom) : 1m 4 bits (max.) l input port ............................................... 8 bits (pull-up resistors are available by mask option) l output port ............................................ 20 bits (can be switched to external memory bus and buzzer output by software) l i/o port .................................................. 20 bits (can be switched to external memory bus and serial i/o by software) l serial interface ...................................... 8-bit clock synchronous type or 8-bit/7-bit asynchronous type can be selected l dot matrix lcd driver ........................... 64 segments 8 commons/16 commons l time base counter ................................ 1 channel for clock use l programmable timer ............................. 8-bit : 1 channel, with event counter function l watchdog timer l programmable svd circuit ................... 16 values programmable (1.05v to 2.60v) l sound generator ................................... with degital envelope function, volume control function (8 levels) l interrupts ............................................... external : input port 2 interrupts internal : clock timer 1 interrupt programmable timer 1 interrupt serial interface 3 interrupts l supply voltage ...................................... 0.9v to 3.6v l current consumption ............................ halt mode (32.768khz or 38khz/1.5v) : 2.0 m a operating mode (32.768khz or 38khz/3.0v) : 7.0 m a l package ................................................ qfp8-160pin (plastic) die form l core cpu architecture l dot matrix lcd driver l serial interface l programmable svd circuit
2 E0C6247 n block diagram com0?5 seg0?3 dd c1? d1 d2 ss ref ram rom 8,192 words x 12 bits system reset control interrupt generator k00?03 k10?13 test p00?03 p10?13 p20?23 p30?33 p40?43 timer programmable timer/counter input port serial interface lcd driver power controller svd output port v v ca?h v v v r00?03 r10?13 r20?23 r30?33 r40?43 i/o port sound generator external memory access function v osc osc1 osc2 osc3 osc4 prescaler 1,792 words x 4 bits 64 x 16 reset core cpu e0c6200a
3 E0C6247 n pin configuration qfp8-160pin v dd v ss v d1 v d2 v c1 ? c5 v ref ca?f cg, ch osc1 osc2 osc3 osc4 k00?03 k10?13 p00?03 p10?13 p20?23 p30?33 p40?43 r00?03 r10?13 r20?23 r30?33 r40 r41?43 com0?om15 seg0?eg63 reset test pin name o i o i o i i i/o i/o i/o i/o i/o o o o o o o o o i i in/out power (+) supply pin power (-) supply pin regulated voltage output pin for oscillation/internal logic boosting/reducing power supply output pin lcd power supply pins, 1/4 bias generated internally, 1/5 bias impressed externally (mask option) lcd power supply test pin capacitor connection pins for lcd booster capacitor connection pins for boosting/reducing power supply crystal osciration input pin crystal oscillation output pin ceramic or cr oscillation input pin (selected by mask option) ceramic or cr oscillation output pin (selected by mask option) input pins input pins i/o pins (switching to external data bus d00?03 is possible by software) i/o pins (switching to external data bus d04?07 is possible by software) i/o pins (switching to chip select cs0?s3 outputs is possible by software) i/o pins ( switching to special output is possible by software: p30/cr, p31/fr, p32/ptovf, p33/fout ) i/o pins (switching to serial i/f input/output is possible by software) output pins (switching to external address bus a00?03 is possible by software) output pins (switching to external address bus a04?07 is possible by software) output pins (switching to external address bus a08?12 is possible by software) output pins (switching to external address bus a13?15 is possible by software) output pin (switching to a16 or wr output is posible by software) output pins (switching to special output is possible by software: r41/rd, r42/bz, r43/bz) lcd common output pins (1/8 or 1/16 duty can be selected by software) lcd segment output pins initial reset input pin test input pin (connect to v dd in normal operation) function 121 127 124 128 129?33 120 141?36 135, 134 126 125 123 122 62?5 66?9 70?3 74?7 84?7 88?1 92?5 96?9 100?03 104?07 108?11 112 113?15 142?49, 61?4 53?, 160?50 119 118 pin no. n pin description 81 120 41 80 index 40 1 160 121 E0C6247 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 seg52 seg51 seg50 seg49 seg48 seg47 seg46 seg45 seg44 seg43 seg42 seg41 seg40 seg39 seg38 seg37 seg36 seg35 seg34 seg33 seg32 seg31 seg30 seg29 seg28 seg27 seg26 seg25 seg24 seg23 seg22 seg21 no. pin name 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 seg20 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0 com15 com14 com13 com12 com11 com10 com9 com8 k00 k01 k02 no. pin name 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 k03 k10 k11 k12 k13 p00 p01 p02 p03 p10 p11 p12 p13 n.c. n.c. n.c. n.c. n.c. n.c. p20 p21 p22 p23 p30 p31 p32 p33 p40 p41 p42 p43 r00 no. pin name 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 r01 r02 r03 r10 r11 r12 r13 r20 r21 r22 r23 r30 r31 r32 r33 r40 r41 r42 r43 n.c. n.c. test reset v ref v dd osc4 osc3 v d1 osc2 osc1 v ss v d2 n.c. : no connection no. pin name 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 v c1 v c2 v c3 v c4 v c5 ch cg cf ce cd cc cb ca com0 com1 com2 com3 com4 com5 com6 com7 seg63 seg62 seg61 seg60 seg59 seg58 seg57 seg56 seg55 seg54 seg53 no. pin name
4 E0C6247 n electrical characteristics l absolute maximum ratings rating symbol unit value supply voltage input voltage (1) input voltage (2) permissible total output current * 1 operating temperature storage temperature soldering temperature / time allowable dissipation * 2 * 1 * 2 v dd v i v iosc s i vdd topr tstg tsol p d v v v ma ? ? mw -0.5 to 7.0 -0.5 to v dd + 0.3 -0.5 to v d1 + 0.3 10 -20 to 70 -65 to 150 260?, 10sec (lead section) 250 (v ss =0v) the permissible total output current is the sum total of the current (average current) that simultaneously flows from the outpu t pins (or is drawn in). in case of plastic package (qfp8-160pin). characteristic symbol unit condition high level input voltage (1) high level input voltage (2) low level input voltage (1) low level input voltage (2) high level input current low level input current (1) low level input current (2) high level output current low level output current common output current segment output current v ih1 v ih2 v il1 v il2 i ih i il1 i il2 i oh1 i ol1 i oh2 i ol2 i oh3 i ol3 v v v v a a a a ma ma ma ma a a a a v ih =1.5v, 3.0v v il1 =v ss without pull up resistor v il2 =v ss with pull up resistor v oh1 =0.9? dd v ol1 =0.1? dd v oh2 =v c5 -0.05v v ol2 =v ss +0.05v v oh3 =v c5 -0.05v v ol3 =v ss +0.05v max. v dd v dd 0.2? dd 0.1? dd 0.5 0 -3 -6 0.3 -1.5 -30 -10 min. 0.8? dd 0.9? dd 0 0 0 -0.5 -8 -16 0.7 6 30 10 k00?3?0?3, p00?3?0?3 p20?3?0?3?0?3 reset, test k00?3?0?3, p00?3?0?3 p20?3?0?3?0?3 reset, test k00?3?0?3, p00?3?0?3 p20?3?0?3?0?3 reset, test k00?3?0?3, p00?3?0?3 p20?3?0?3?0?3 reset, test k00?3?0?3, p00?3?0?3 p20?3?0?3?0?3 reset, test r00?3?0?3?0?3?0?3 r40?3, p00?3?0?3?0?3 p30?3?0?3 r00?3?0?3?0?3?0?3 r40?3, p00?3?0?3?0?3 p30?3?0?3 com0?5 seg0?3 (unless otherwise specified, the values listed below are standard values under the following conditions: v dd =1.5/3.0v, v ss =0v, f osc1 =32.768khz, ta=25 c, v d1 /v c1 /v c2 /v c4 /v c5 are internal voltage , c1?8=0.2 f, c9?10=0.4 f) typ. -5 -10 v dd = 1.5v 3.0v v dd = 1.5v 3.0v v dd = 1.5v 3.0v l dc characteristics l recommended operating conditions condition symbol unit remark supply voltage oscillation frequency (1) oscillation frequency (2) * 1 * 2 v dd f osc1 f osc3 v v v v v khz khz khz khz khz khz v ss =0v any one is selected either one is selected duty 50?% max. 1.25 2.2 3.6 3.6 3.6 260 1,200 typ. 1.1 1.5 3.0 3.0 3.0 32.768 38.400 50.000 76.800 200 1,000 min. 0.9 0.9 1.25 2.2 2.6 50 50 boost mode boost mode normal mode normal mode reduce mode vdc0, 1 = "1" vdc0, 1 = "2" or "3" 1mhz oscillation cannot be performed. 200khz or 1mhz oscillation can be performed. (osc3: off) (osc3: on * 1 ) (osc3: off) (osc3: on * 2 ) (osc3: off)
5 E0C6247 l analog circuit characteristics and current consumption characteristic symbol unit condition lcd drive voltage (when v c1 standard is selected) lcd drive voltage (when v c2 standard is selected) v c1 v c2 v c4 v c5 v c1 v c2 v c4 v c5 v v v v v v v v connect 1m w load resistor between v ss and v c1 (without panel load) v dd =1.5v connect 1m w load resistor between v ss and v c2 (without panel load) connect 1m w load resistor between v ss and v c4 (without panel load) connect 1m w load resistor between v ss and v c5 (without panel load) connect 1m w load resistor between v ss and v c1 (without panel load) connect 1m w load resistor between v ss and v c2 (without panel load) v dd =3.0v connect 1m w load resistor between v ss and v c4 (without panel load) connect 1m w load resistor between v ss and v c5 (without panel load) max. typ. 1.12 2? c1 0.9 3? c1 0.9 4? c1 0.9 1/2? c2 0.95 typ. 1.12 3/2? c2 0.95 2? c2 0.95 typ. 0.975 0.990 1.005 1.020 1.035 1.050 1.065 1.080 1.095 1.110 1.125 1.140 1.155 1.170 1.185 1.200 1.95 1.98 2.01 2.04 2.07 2.10 2.13 2.16 2.19 2.22 2.25 2.28 2.31 2.34 2.37 2.40 min. typ. 0.88 2? c1 3? c1 4? c1 1/2? c2 -0.1 typ. 0.88 3/2? c2 2? c2 lc0?="0" lc0?="1" lc0?="2" lc0?="3" lc0?="4" lc0?="5" lc0?="6" lc0?="7" lc0?="8" lc0?="9" lc0?="10" lc0?="11" lc0?="12" lc0?="13" lc0?="14" lc0?="15" lc0?="0" lc0?="1" lc0?="2" lc0?="3" lc0?="4" lc0?="5" lc0?="6" lc0?="7" lc0?="8" lc0?="9" lc0?="10" lc0?="11" lc0?="12" lc0?="13" lc0?="14" lc0?="15" (unless otherwise specified, the values listed below are standard values under the following conditions: v dd =1.5v / when v c1 standard is selected , v dd =3.0v / when v c2 standard is selected , v ss =0v, f osc1 =32.768khz, c g =25pf, ta=25 c, v d1 /v c1 /v c2 /v c4 /v c5 are internal voltage , c1?8=0.2 f, c9?10=0.4 f)
6 E0C6247 characteristic symbol unit condition svd voltage svd circuit response time power current consumption * 1 v svd t svd i op v sec a a a a a a a a a a a a a a a a a a a a a a a a a svds0?="0" svds0?="1" svds0?="2" svds0?="3" svds0?="4" svds0?="5" svds0?="6" svds0?="7" svds0?="8" svds0?="9" svds0?="10" svds0?="11" svds0?="12" svds0?="13" svds0?="14" svds0?="15" during halt normal mode lcd power off during halt normal mode * 1 lcd power on during halt boost mode * 1 v dd =1.2v, lcd power on during halt reduce mode * 1 v dd =3.0v, lcd power on during execution normal mode * 1 lcd power on during execution boost mode * 1 v dd =1.2v, lcd power on during execution reduce mode * 1 v dd = 3.0v, lcd power on max. typ. min. 32.768khz 50.0khz 76.8khz 32.768khz 50.0khz 76.8khz 32.768khz 50.0khz 76.8khz 32.768khz 50.0khz 76.8khz 32.768khz 50.0khz 76.8khz 200khz(cr oscillation) 870khz(cr oscillation) 1mhz(ceramic oscillation) 32.768khz 50.0khz 76.8khz 200khz(cr oscillation) 32.768khz 50.0khz 76.8khz (unless otherwise specified, the values listed below are standard values under the following conditions: v dd =3.0v, v ss =0v, f osc1 =32.768khz, c g =25pf, ta=25 c, v d1 /v c1 /v c2 /v c4 /v c5 are internal voltage , c1?8=0.2 f, c9?10=0.4 f) 1.15 1.15 1.20 1.25 1.30 1.35 1.45 1.65 2.00 2.05 2.10 2.15 2.25 2.35 2.55 2.65 100 4.0 5.0 5.6 10.0 14.0 18.0 25.0 30.0 38.0 8.0 11.0 14.0 18.0 24.0 32.0 100 600 500 36.0 48.0 64.0 200 14.0 18.0 25.0 1.05 1.10 1.15 1.20 1.25 1.30 1.40 1.60 1.95 2.00 2.05 2.10 2.20 2.30 2.50 2.60 2.0 2.3 3.0 6.5 8.0 11.0 13.5 16.0 22.0 5.0 6.5 9.0 10.0 13.0 19.0 40 330 300 20.0 26.0 37.0 80 7.0 10.0 14.0 0.95 1.05 1.10 1.15 1.20 1.25 1.35 1.55 1.90 1.95 2.00 2.05 2.15 2.25 2.45 2.55 without panel load. the svd circuit is turned off.
7 E0C6247 l oscillation characteristics the oscillation characteristics change depending on the conditions (components used, board pattern, etc.). use the follow- ing characteristics as reference values. osc1 crystal oscillation circuit characteristic symbol unit condition oscillation start voltage oscillation stop voltage built-in capacitance (drain) frequency/voltage deviation frequency/ic deviation frequency adjustment range harmonic oscillation start voltage permitted leak resistance vsta vstp c d f/v f/ic f/c g v hho r leak v v v pf ppm ppm ppm ppm ppm v m w t sta 3sec t stp 10sec (v dd ) including the parasitic capacitance inside the ic (in chip) v dd =0.9 to 3.6v c g =5 to 25pf c g =5pf between osc1 and v dd , v ss max. 5 10 10 min. 1.1 1.1 0.9 -10 35 25 3.6 200 (v dd ) normal mode boost mode with vdc switching without vdc switching 32.768, 38.4, 50khz 76.8khz (v dd ) (unless otherwise specified, the values listed below are standard values under the following conditions: v dd =3.0v, v ss =0v, f osc1 =32.768khz, c g =25pf, c d =built-in, ta=25 c) typ. 14 45 35 osc3 cr oscillation circuit 1 (200khz) oscillation frequency dispersion oscillation start voltage oscillation start time oscillation stop voltage * 1 f osc3 vsta t sta vstp % v msec v normal mode (v dd ) v dd =2.2 to 3.6v normal mode (v dd ) max. 30 3 min. -30 2.2(0.9) * 1 2.2(0.9) * 1 (unless otherwise specified, the values listed below are standard values under the following conditions: v dd =3.0v, v ss =0v, r cr =160k w , ta=25?) typ. 200khz characteristic symbol unit condition items enclosed in parentheses ( ) is those used in the boost mode. osc3 cr oscillation circuit 2 (1mhz) oscillation frequency dispersion oscillation start voltage oscillation start time oscillation stop voltage f osc3 vsta t sta vstp % v msec v normal mode (v dd ) v dd =2.2 to 3.6v normal mode (v dd ) max. 30 3 min. -30 2.2 2.2 (unless otherwise specified, the values listed below are standard values under the following conditions: v dd =3.0v, v ss =0v, r cr =33k w , ta=25?) typ. 870khz characteristic symbol unit condition osc3 ceramic oscillation circuit (1mhz) oscillation start voltage oscillation start time oscillation stop voltage vsta t sta vstp v msec v normal mode (v dd ) v dd =2.2 to 3.6v normal mode (v dd ) max. 5 min. 2.2 2.2 (unless otherwise specified, the values listed below are standard values under the following conditions: v dd =3.0v, v ss =0v, ceramic oscillator: 1mhz, c gc =c dc =100pf, ta=25?) typ. characteristic symbol unit condition cr oscillation frequency - resistance characteristics <200khz> 10 20 50 100 200 100 200 500 1,000 2,000 30 40 external resistance r cr [k w ] oscillation frequency f osc3 [khz] <1mhz> 50 100 200 500 50 100 200 500 40 30 external resistance r cr [k w ] oscillation frequency f osc3 [khz]
8 E0C6247 l external memory access ac characteristics read cycle ? during 32khz (osc1) operation symbol min. typ. max. unit csx set-up time in read cycle csx hold time in read cycle rd set-up time in read cycle rd hold time in read cycle t ras t rah t rds t rdh sec sec sec sec (condition: v dd =1.5v, v ss =0v, ta=25 c, v ih =0.8v dd , v il =0.2v dd , v oh =0.8v dd , v ol =0.2v dd , c l =100pf [load capacitance]) 0.15 t c 0 0.15 t c 0 characteristic ? during 1mhz (osc3) operation write cycle ? during 32khz (osc1) operation ? during 1mhz (osc3) operation symbol min. typ. max. unit csx set-up time in read cycle csx hold time in read cycle rd set-up time in read cycle rd hold time in read cycle t ras t rah t rds t rdh nsec nsec nsec nsec (condition: v dd =3.0v, v ss =0v, ta=25?, v ih =0.8v dd , v il =0.2v dd , v oh =0.8v dd , v ol =0.2v dd , c l =100pf [load capacitance]) 0.15 t c 0 0.15 t c 0 characteristic min. typ. max. address set-up time in write cycle address hold time in write cycle write signal pulse width data output set-up time in write cycle data output hold time in write cycle t was t wah t wp t wds t wdh sec sec sec sec sec 0 5 5 5 530 symbol unit (condition: v dd =1.5v, v ss =0v, ta=25 c, v ih =0.8v dd , v il =0.2v dd , v oh =0.8v dd , v ol =0.2v dd , c l =100pf [load capacitance]) characteristic min. typ. max. address set-up time in write cycle address hold time in write cycle write signal pulse width data output set-up time in write cycle data output hold time in write cycle t was t wah t wp t wds t wdh nsec nsec nsec nsec nsec 0 200 200 200 200 1,500 symbol unit (condition: v dd =3.0v, v ss =0v, ta=25?, v ih =0.8v dd , v il =0.2v dd , v oh =0.8v dd , v ol =0.2v dd , c l =100pf [load capacitance]) characteristic clk (sysyem clock) csx rd din csx wr dout v ih v il t c t rah v ih v il v oh v ol t wah t wdh t wds v ih v il t wp t ras t rdh t rds t was v oh v ol v oh v ol v oh v ol * 1/ t c: oscillation frequency
9 E0C6247 l serial interface ac characteristics clock synchronous master mode ? during 32khz (osc1) operation ? during 1mhz (osc3) operation clock synchronous slave mode ? during 32khz (osc1) operation ? during 1mhz (osc3) operation asynchronous mode sclk out sout sin v oh v oh v ol t sms t smh t smd v ih1 v il1 v ol sclk in sout sin v ih1 v oh v ol t sss t ssh t ssd v ih1 v il1 v il1 sin t sa 1 start bit sampling clock erroneous start bit detection signal stop bit t t sa 2 min. typ. max. transmitting data output delay time receiving data input set-up time receiving data input hold time t smd t sms t smh sec sec sec 10 5 5 symbol unit (condition: v dd =1.5v, v ss =0v, ta=25 c, v ih1 =0.8v dd , v il1 =0.2v dd , v oh =0.8v dd , v ol =0.2v dd ) characteristic min. typ. max. transmitting data output delay time receiving data input set-up time receiving data input hold time t smd t sms t smh nsec nsec nsec 400 200 200 symbol unit (condition: v dd =3.0v, v ss =0v, ta=25?, v ih1 =0.8v dd , v il1 =0.2v dd , v oh =0.8v dd , v ol =0.2v dd ) characteristic min. typ. max. transmitting data output delay time receiving data input set-up time receiving data input hold time t ssd t sss t ssh sec sec sec 10 5 10 symbol unit (condition: v dd =1.5v, v ss =0v, ta=25 c, v ih1 =0.8v dd , v il1 =0.2v dd , v oh =0.8v dd , v ol =0.2v dd ) characteristic min. typ. max. transmitting data output delay time receiving data input set-up time receiving data input hold time t ssd t sss t ssh nsec nsec nsec 400 200 500 symbol unit (condition: v dd =3.0v, v ss =0v, ta=25 c, v ih1 =0.8v dd , v il1 =0.2v dd , v oh =0.8v dd , v ol =0.2v dd ) characteristic min. typ. max. start bit detection error time * 1 erroneous start bit detection range time * 2 * 1 * 2 t sa 1 t sa 2 sec sec 0 9t/16 t/16 10t/16 symbol unit (condition: v dd =1.5v, v ss =0v, ta=25?) characteristic start bit detection error time is a logical delay time from inputting the start bit until internal sampling begins operating. (time as far as ac is excluded.) erroneous start bit detection range time is a logical range to detect whether a low level (start bit) has been input again afte r a start bit has been detected and the internal sampling clock has started. when a high level is detected, the start bit detection circuit i s reset and goes into a wait status until the next start bit. (time as far as ac is excluded.)
10 E0C6247 l timing chart supply voltage reset terminal internal reset signal note) 3 msec when f osc1 = 76.8 khz 3 sec (high active) (low active) (high active) 1.5 msec note) osc1 oscillation circuit output clock oscillation detection circuit output oscillation is in unstabilized state dbon vdsel vcsel note) heavy load on off note) vcsel is used only when it is required. * * 100 msec or more 100 msec or more 1 msec or more 2 sec or more * : more than 1 instruction execution time hlon note) vdsel note) vdc1 vdc0 oscc clkchg * * 2.5 msec or more * 100 msec or more 2.5 msec or more 5 msec or more * 2.5 msec or more * note) * : more than 1 instruction execution time when the reduce mode is used. however, when using the reduce mode in the lcd system voltage circuit (vcsel = "1"), hlon should be set to "1". * * * * dbon note) vdsel note) vdc1 (all 0) vdc0 oscc clkchg note) use dbon and vdsel only when changes are required. 100 msec or more * 2.5 msec or more 5 msec or more * : more than 1 instruction execution time 1. initial reset 4. boost mode setting when driving heavy load 3. osc1 ? osc3 (1mhz) switching 2. osc1 ? osc3 (200khz) switching
11 E0C6247 n basic external connection diagram ca cb cc cd ce cf cg ch v v v dd d1 d2 osc1 osc2 osc3 osc4 reset v ss c1 c2 c3 c9 c4 c10 c11 c gx c dc c cp 0.9v | 3.6v + x'tal cr * 1 * 2 r cr k00?03 k10?13 p00?03 p10?13 p20 p21 p22 p23 p30 p31 p32(ptovf) p33(fout) p40 (sin) p41 (sout) p42 (sclk) p43 (srdy) r00?03 r10?13 r20?23 r30?33 r40 r41 seg0 | seg63 com0 | com15 c5 c6 c7 c8 E0C6247 lcd panel 64 16 * 1: ceramic oscillation * 2: cr oscillation c gc v ref test v v v v v c1 c2 c3 c4 c5 r42(bz) r43(bz) piezo r a1 r a2 input i/o output crystal oscillator trimmer capacitor ceramic oscillator gate capacitor drain capacitor resistor for cr oscillation protection resistors capacitors capacitors capacitor capacitor x'tal c gx cr c gc c dc r cr r a1 , r a2 c1?8 c9, c10 c11 cp 32.768khz / 38.4khz / 50.0khz / 76.8khz, ci (max.) = 35k w 5?5pf 1mhz (3.0v) 100pf 100pf 160k w (200khz), 33k w (1mhz) 100 w 0.2 f 0.4 f 0.1 f 3.3 f note: the above table is simply an example, and is not guaranteed to work.
E0C6247 notice: no part of this material may be reproduced or duplicated in any form or by any means without the written permission of seiko ep son. seiko epson reserves the right to make changes to this material without notice. seiko epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is n o representation that this material is applicable to products requiring high level reliability, such as, medical products. moreover, no license to an y intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accord ance with this material will be free from any patent or copyright infringement of a third party. this material or portions thereof may contain technology or the subject relating to strategic products under the control of the foreign exchange and foreign trade control law of japan and may require an export license from the ministry of international trade and industry or other approval from another government agency. ? seiko epson corporation 1999 all right reserved. seiko epson corporation electronic devices marketing division ic marketing & engineering group ed international marketing department i (europe & u.s.a.) 421-8, hino, hino-shi, tokyo 191-8501, japan phone : 042-587-5812 fax : 042-587-5564 ed international marketing department ii (asia) 421-8, hino, hino-shi, tokyo 191-8501, japan phone : 042-587-5814 fax : 042-587-5110 n package dimensions plastic qfp8-160pin 28 ?.1 31.2 ?.4 81 120 28 ?.1 31.2 ?.4 41 80 index 0.3 ?.1 40 1 160 121 3.35 ?.1 0.1 3.65 max 0.6 ?.2 0 10 0.15 ?.05 0.65 1.6 unit: mm

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